Method based on backboard transmitting time division multiplexing circuit data and a bridge connector

ABSTRACT

The invention discloses a method for multi-path TDM data transmission based on backplane and a TDM bridge connector for implementing the method. The method includes: applying a high-speed serial line on backplane to connect a center switch network board and service boards; multiplexing or interleaving multi-path TDM data at transmitting side, and then transmitting in batch to said high-speed serial line on the backplane; at receiving side, serial receiving said data and de-multiplexing or de-interleaving them to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity on backplane and looses the requirement of clock synchronization, so the system reliability is greatly raised.

FIELD OF THE TECHNOLOGY

[0001] The invention generally relates to the time division multiplexing(TDM) technology, specifically to a TDM data transmission method on thebackplane and a TDM bridge connector thereof.

BACKGROUND OF THE INVENTION

[0002] Along with the differential signal level getting lower, noiseimmunity and transmission rate are getting higher, it is required thatthe transmission capacity should be getting higher. Traditionally, theTDM centralized switching structure is shown in FIG. 1, where everyservice board shares the TDM bus 12, and the center switch network boarddistributes clock, for data transmission at backplane circuit, to eachservice board with a point-to-point mode or a bus mode.

[0003] Suppose that clock high-level duration is t, data is transmittedat leading edge of the clock and is sampled at falling edge of theclock, then the time sequence difference of the traditional synchronousdata transmission based on backplane is shown in FIG. 2, where phasebetween the frame synchronization signal and the clock is not aligned.As shown in FIG. 2 the frame synchronization signal between the centerswitch network board and the service boards has to time delay and sodoes the clock between the center switch network board and the serviceboards, transmission time for data from the center switch network boardto the service boards is t₂=t+t₀ and transmission time for data from theservice boards to the center switch network board is only t₁=t−t₀.Obviously, the transmission time is asymmetric, and when thetransmission frequency is very high, the system reliability is greatlyreduced, which means that the system capacity cannot be furtherincreased. Therefore, clock synchronization is a bottleneck oftraditional data transmission based on backplane bus with strictsynchronization.

[0004] Since the distance and distributed parameters between differentslots of the backplane are different, the time delay for different slotsis different. There are disadvantages for the bus mode of signaltransmission: a large area, a long distance, many slots, density pins,serious switching noise and electromagnetic interference (EMI) etc.,when they are not dealt with adequately, there will be seriously signalreflection and interference that cause signal distortion. In this case,the transmission rate is limited for the system reliability.

[0005] In order to increase transmission capacity of backplane circuit,increasing number of transmission signals is a fundamental method, butthis is cost by system complexity and lead to loss of reliability andperformance of work, and the number of transmission signals islimitation.

[0006] In summary, the disadvantages of traditional TDM bus datatransmission based on backplane is as following:

[0007] 1) it is required strict synchronization, i.e. phase between theframe signal and clock signal should be aligned more strictly;

[0008] 2) There are disadvantages for the bus mode of signaltransmission: a large area, a long distance, many slots, density pins,serious switching noise and electromagnetic interference (EMI) etc.Strict synchronization is very difficult. The transmission rate isgreatly limited in order to guarantee system reliability;

[0009] 3) no matter the clock signal is distributed with point-to-pointmode or bus mode, since the distance and distributed parameters betweendifferent slots are different, the time delay is different;

[0010] 4) In order to increase transmission capacity of backplanecircuit, increasing number of transmission signals is a fundamentalmethod, but this is cost by system complexity and lead to loss ofreliability and performance of work, and the number of transmissionsignals is limitation.

SUMMARY OF THE INVENTION

[0011] Considering what have been mentioned above, the inventionprovides a method for multi-path TDM data transmission based onbackplane and a bridge connector thereof in order to reducesynchronization requirement of the clock, increase transmission rate atthe backplane circuit and switching capacity, and raise datatransmission quality and reliability.

[0012] A method for multi-path TDM data transmission on the backplanecomprising:

[0013] A) applying a high-speed serial line on the backplane to connectthe center switch network board with each service board;

[0014] B) multi-path TDM data is multiplexed or interleaved at thetransmitting side, and then transmitted in batch to said high-speedserial line on the backplane; at the receiving side, data are serialreceived and de-multiplexed to every TDM path.

[0015] According to the method, step B includes: at the transmittingside, the multi-path TDM data are multiplexed or interleaved by taking aframe as a unit, and then transmitted in batch to said high-speed serialline on the backplane; at the receiving side, data received by thehigh-speed serial line are de-multiplexed or de-interleaved to every TDMpaths by taking a frame as a unit; said data serial transmitting andreceiving takes the TDM clock as sampling clock.

[0016] According to the method, step B includes: at the transmittingside, the multi-path TDM data are multiplexed or interleaved by taking atime-slot as a unit, and then transmitted in batch to said high-speedserial line on the backplane; at the receiving side, data received bythe high-speed serial line are de-multiplexed or de-interleaved to everyTDM path by taking a time-slot as a unit; said data serial transmittingand receiving takes the TDM clock as sampling clock.

[0017] According to the method, step B includes: at the transmittingside, the multi-path TDM data are multiplexed or interleaved by taking abit as a unit, and then transmitted in batch to said high-speed serialline on the backplane; at the receiving side, data received by thehigh-speed serial line are de-multiplexed or de-interleaved to every TDMpath by taking a bit as a unit; said data serial transmitting andreceiving takes n multiple of TDM clock as sampling clock, wherein n isan integer greater than zero.

[0018] The multiplexing and interleaving of the multi-path TDM data,mentioned above, can also be done by a high-speed serial driver thatmakes parallel-to-serial conversion, and then sent to the high-speedserial line on the backplane at the transmitting side; at the receivingside, the high-speed serial driver synchronously receives the data andmakes serial-to-parallel conversion to sample data for every TDM pathaccording to the TDM frame synchronization.

[0019] According to the method, said TDM frame synchronization signaland clock signal at the receiving side can be distributed by apoint-to-point mode or a bus mode.

[0020] A method for implementing said TDM Bridge connector includes:

[0021] A TDM high-speed serial transmitting adaptive circuit, whichconnects with the data signal of the TDM switching circuit on itsreceiving end and the high-speed serial line on the backplane on itstransmitting end, receives a multi-path TDM data from the TDM switchingcircuit, and after multiplexing or interleaving and adapting they aresent to the high-speed serial line on the backplane;

[0022] A TDM high-speed serial receiving adaptive circuit, whichconnects with the high-speed serial line on its receiving end and thedata line of the TDM switching circuit on its transmitting end, receivesserial the serial data sent from the high-speed serial line, and afteradapting and de-multiplexing or de-interleaving they are sent to the TDMswitching circuit;

[0023] And a clock control circuit, which is connected with the clockand sync signal of the TDM switching circuit, provides clock and syncsignal.

[0024] According to the TDM bridge connector of the invention, saidhigh-speed serial transmitting adaptive circuit further includes: a TDMreceiving interface that connects with the data signal of the TDMswitching circuit to receive the multi-path TDM data; astore-and-forward circuit that converts the received multi-path TDM datato one line serial data; a high-speed serial transmitting interface thatconnects with the high-speed serial line on the backplane to adapt andsend the serial data to the high-speed serial line; said high-speedserial receiving adaptive circuit further includes: a high-speed serialreceiving interface that connects with the high-speed serial line on thebackplane to receive the serial data from the high-speed serial line; astore-and-forward circuit that converts the received serial data tomulti-path TDM data; and a TDM transmitting interface that connects withthe TDM switching circuit for sending the TDM data to the TDM switchingcircuit.

[0025] According to the TDM bridge connector of the invention, saidhigh-speed serial transmitting adaptive circuit further includes: a TDMreceiving interface that connects with the data signal of the TDMswitching circuit to receive the multi-path TDM data; aparallel-to-serial circuit that converts the received multi-path TDMdata to one line serial data; a high-speed serial transmitting interfacethat connects with the high-speed serial line on the backplane to adaptand send the serial data to the high-speed serial line; said high-speedserial receiving adaptive circuit further includes: a high-speed serialreceiving interface that connects with the high-speed serial line on thebackplane to receive the serial data from the high-speed serial line; aserial-to-parallel circuit that converts the received serial data tomulti-path TDM data; and a TDM transmitting interface that connects withthe TDM switching circuit for sending the TDM data to the TDM switchingcircuit.

[0026] Said high-speed serial transmitting adaptive circuit furtherincludes a clock multiple frequency circuit that provides a multiplefrequency of the clock signal acting as a clock for the high-speedserial data transmission; said high-speed serial receiving adaptivecircuit further includes a multiple frequency of the clock signal as aclock for the high-speed serial data receiving.

[0027] Furthermore, the high-speed serial receiving adaptive circuit canalso include a store-and-forward circuit; and the high-speed serialtransmitting adaptive circuit includes a clock multiple frequencycircuit that provides a multiple frequency of the TDM switching circuitclock signal as a clock signal for transmitting high-speed serial data.

[0028] Said high-speed serial line includes a downward transmission linefrom the center switch network board to the service boards and an upwardtransmission line from the service boards to the center switch networkboard.

[0029] Said high-speed serial line includes. a TDM data sending line, aTDM data receiving line, a TDM frame sync line and a clock line.

[0030] The invention takes a high-speed serial line on backplane toconnect the center switch network board and every service board and tomultiplex or interleave/de-multiplex or de-interleave the multi-path TDMdata for transmission in batch; in this way, the transmission rate andswitching capacity on backplane are greatly increased and at the sametime the accurate requirement of the transmission clock phase isdecreased, and source of signals on backplane is saved; in addition,because of using the differential transmission mode the noiseinterference and EMI are reduced. Consequently, data transmissionquality and reliability of the system is greatly increased.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031]FIG. 1 shows a diagram of the traditional TDM concentratedswitching structure.

[0032]FIG. 2 shows a time delay of the traditional TDM clockconcentrated distributing.

[0033]FIG. 3 shows the diagram of a TDM concentrated switching withhigh-speed serial line.

[0034]FIG. 4 shows the diagram of a TDM switching with TDM bridgeconnector.

[0035]FIG. 5 shows an embodiment of the TDM bridge connector.

[0036]FIG. 6 shows the diagram of connection between the center switchnetwork board and service boards in the FIG. 5 embodiment.

[0037]FIG. 7 shows a time sequence diagram for multi-path datatransmission when taking a frame as a unit.

[0038]FIG. 8 shows a time sequence diagram for multi-path datatransmission when taking a time-slot as a unit.

[0039]FIG. 9 shows the diagram of a high-speed serial driver.

[0040]FIG. 10 shows the diagram of connection between the center switchnetwork board and service boards in the FIG. 9 embodiment.

[0041]FIG. 11 shows a time sequence diagram of multi-path datatransmission by using synchronous multiplexing/de-multiplexing.

[0042]FIG. 12 shows the diagram of connection between the center switchnetwork board and service boards by using synchronous transmission andstore-and-forward for multi-path data transmission.

[0043]FIG. 13 shows the diagram of connection between the center switchnetwork board and service boards by using synchronous transmission andstore-and-forward for multi-path data transmission and adding a clockdouble frequency circuit.

[0044]FIG. 14 shows a time sequence diagram of using synchronoustransmission and store-and-forward for multi-path data transmission.

EMBODIMENTS OF THE INVENTION

[0045] The invention will be described in more detail with reference tothe drawings.

[0046]FIG. 3 shows a diagram of the invention for TDM concentratedswitching with high-speed serial line. The clock circuit 101 of thecenter switch network board 10 provides synchronous and clock signal,which can be distributed by point-to-point mode or bus mode, to serviceboards 11. Between the TDM switching circuit 102 and the service boards11 there is a high-speed serial line 13 for data transmission withpoint-to-point mode.

[0047]FIG. 4 shows a TDM switching structure with TDM bridge connectorfor the invention. Data, clock and sync signals of the TDM switchingcircuit 102 are all connected to the TDM bridge connector 14. Aftermultiplexed/de-multiplexed, the TDM data from the TDM switching circuitare transmitted by the TDM bridge connector 14 through the high-speedserial line 13 on the backplane.

[0048] The TDM bridge connector 14 includes: a TDM high-speed serialtransmitting adaptive circuit connected with the data signal of the TDMswitching circuit on the one end and with the high-speed serial line atthe backplane on the another end, which receives multi-path TDM datatransmitted by the TDM switching circuit and sends them to thehigh-speed serial lines after multiplexing or interleaving and adapting;a high-speed serial receiving adaptive circuit connected with thehigh-speed serial lines on the one end and with the data signal of theTDM switching circuit on the other end, which receives serial datatransmitted by the high-speed serial line and sends them to the TDMswitching circuit after adapting and de-multiplexing or de-interleaving;and a clock control circuit connected with the clock and sync signals ofthe TDM switching circuit, which generates clock and sync signals.

[0049]FIG. 5 shows an embodiment of the TDM bridge connector 14. The TDMhigh-speed serial transmitting adaptive circuit includes: a TDMreceiving interface 141, which is connected with the data signal of theTDM switching circuit to receive the multi-path TDM data; astore-and-forward circuit 142, which converts the received multi-pathTDM data into one-path serial data; and a high-speed serial transmittinginterface 143, which is connected with the high-speed serial line 13 onthe backplane to make adaptation for the serial data and send them tothe high-speed serial line. The high-speed serial receiving adaptivecircuit includes: a high-speed serial interface 144, which is connectedwith the high-speed serial line 13 and receives the high-speed serialdata; a store-and-forward circuit 145, which converts the receivedserial data into multi-path TDM data; and a TDM transmitting interface146, which is connected with the TDM switching circuit to send themulti-path TDM data.

[0050] The clock control circuit 140 is connected with the clock andsync signals of the TDM switching circuit and provides the clock signalto the TDM high-speed serial transmitting adaptive circuit and the TDMhigh-speed serial receiving adaptive circuit.

[0051]FIG. 6 shows a block diagram of the center switch network boardand a service board with the FIG. 5 embodiment. Taking a frame as aunit, FIG. 7 shows a time sequence for the multi-path data transmission.The center switch network board provides high-way (HW) sync and clocksignals to every service board, and the data is transmitted at theleading edge of the clock and sampled at the falling edge of the clock.It can be seen from the FIG. 7 that when the time T is guaranteed,reliability of data transmission is guaranteed too and it is insensitiveto the clock delay. Therefore, when transmission quality of the clock issatisfied the system requirement, distribution of the clock can be apoint-to-point mode or a bus mode.

[0052] Suppose the bandwidth of the high-speed serial line is 200 Mbps,when combining six data signals and each of them being 32M, thebandwidth 6×32=192 Mbps are occupied. So, there is enough redundancy forincreasing the traffic of each service board when using the high-speedserial line for transmission.

[0053] In FIG. 7, the Fri (i=1, 2, 3 . . . ) represents frames, it is ntimes of the usual TDM period of a frame, wherein frequency of the framecan be 8 k i.e. 8 k frame, n is a integer greater than zero; forexample, the period of 8 k frame is 125 μs, the period of Fri can be 125μs, 250 μs or 375 μs etc. depending on the system design. The datatransmission procedure on the high-speed serial line of FIG. 7 is as thefollowings:

[0054] 1) During the first frame, i.e. FR1, the adaptive circuit of thehigh-speed serial line on the sending end assembles all HWs data in theFR1.

[0055] 2) During second frame, i.e. FR2, the adaptive circuit ofhigh-speed serial line on the sending end sends the FR1 data to theadaptive circuit of high-speed serial line on the receiving end throughthe high-speed serial line.

[0056] 3) During third frame, i.e. FR3, the adaptive circuit of thehigh-speed serial line on the receiving end de-multiplexes the receivedFR1 data and sends to corresponding HW, respectively. FR1 data istransferred to the TDM switching circuit of the destination board.

[0057] Really, the data transmission procedure mentioned above is abatching transmission procedure taking a frame as a unit.

[0058] The disadvantage of high-speed serial data transmission with aframe as a unit is that there is a two-frame fixed time delay. Whenusing multi-frame multiplexing, i.e. taking n frames as a unit for everyHW, or interleaved multiplexing, i.e. interleaving multiple HWs data inframes accordingly; the time delay will be n times of the single framemultiplexing. So, it is right in theory but inapplicable forimplementation.

[0059]FIG. 8 shows a time sequence for the multi-path data transmissionwhen taking a time-slot as a unit. The central switching board providesthe frame synchronization signal and clock signal to HWs of everyservice board; and the data is transmitted at leading edge of the clockand sampled at falling edge of the clock. It can be seen from FIG. 8that the data transmission is reliable only requiring that the time T inFIG. 8 to be guaranteed; and the data transmission is insensible to theclock delay. Consequently, when transmission quality of the clock issatisfied the system requirement, the clock distribution can be apoint-to-point mode or a bus mode.

[0060] Suppose the bandwidth of the high-speed serial line is 200 Mbps,it can combine five data signals and each of them is 32M, and thebandwidth 5×32=160 Mbps are occupied. So, there is enough redundancy forincreasing the traffic of each service board when using the high-speedserial line for transmission.

[0061] In FIG. 8 the FRAME represents a frame, which is 8 k frame andhas a period of 125 μs; the TS is a time-slot, which is an integermultiple of the usual TDM time-slot. For example, a 2M HW has atime-slot of eight clocks time, and the TS can be 16 clocks time or 24clocks time etc. depending on the system design. The data transmissionprocedure on the high-speed serial line of FIG. 8 is as the following:

[0062] 1)During the first time-slot, i.e. TS1, the adaptive circuit ofthe high-speed serial line on the sending end assembles all HWs data inthe TS1.

[0063] 2)During second time-slot, i.e. TS2, the adaptive circuit ofhigh-speed serial line on the sending end sends the TS1 data to theadaptive circuit of high-speed serial line on the receiving end throughthe high-speed serial line.

[0064] 3)During third TS, i.e. TS3, the adaptive circuit of thehigh-speed serial line on the receiving end de-multiplexes the receivedTS1 data and sends to corresponding HW, respectively. TS1 data istransferred to the TDM switching circuit of the destination board.

[0065] Really, the data transmission procedure mentioned above is abatching transmission procedure taking a time-slot as a unit.

[0066] The disadvantage of the data transmission with a time-slot as aunit is that each transfer will bring in a two time-slots fixed timedelay, as shown in FIG. 8. Since the data pass the center switch networkboard twice, there are four time-slots fixed time delay, i.e. 4×Tts,wherein the Tts is a time-slot period. As the data stream has a twotime-slots shift, data stream at the interface devices of thetransmitter and receiver of the boards has phase differences; it isnecessary to have a phase adjusting circuit in front of the interfacedevice to guarantee that the phases are coincidence.

[0067] In the above multi-path TDM data transmission, themultiplexing/de-multiplexing is implemented at the store-and-forwardcircuit; it can also be implemented with aparallel-to-serial/serial-to-parallel circuit. FIG. 9 shows a TDM bridgeconnector implemented with the high-speed serial drivers: the serialtransmitter DS92LV1021 (151) and the serial receiver DS92LV1212 (152) ofthe National Semiconductor (NS) Company products.

[0068]FIG. 10 shows a block diagram of a center switch network board anda service board for data transmission, where high-speed serial driversimplement the TDM bridge connector. When the multi-path datatransmission applies a synchronous multiplexing/de-multiplexing mode,the time sequence is shown in FIG. 11. The clock distribution can be apoint-to-point mode or a bus mode when transmission quality of clock issatisfied the system requirement. The clock circuit 101 on the centerswitch network board 10 provides to every service board the HW framesynchronous signal and HW clock signal, and data is transmitted at theleading edge and sampled at the falling edge of the HW clock signal. Itcan be seen from FIGS. 10 and 11, the multiple frequency circuit 16generates n multiple HW clock (n is a integer greater than 0). On thetransmitting end, the high-speed serial driver 15 samples the HWs dataand sends them to the high-speed serial line 13 at the leading edge ofthe multiple frequency clock; and on the receiving end, the TDMswitching circuit samples the data outputted from the high-speed serialdriver 15 at the falling edge of the HW clock.

[0069]FIG. 11 shows a three multiple HW clock case. At the sending end,after t1 duration when the TDM switching circuit sent the HW data, thehigh-speed serial driver samples data at the leading edge of themultiple frequency clock and sends them to the high-speed serial line;and at the receiving end, the TDM switching circuit samples data at thefalling edge of the HW clock and there is t2 duration in between. Thedisadvantage of the synchronous multiplexing/de-multiplexing mode isthat the huge capacity of the high-speed serial line cannot be usedthoroughly. At present the point-to-point high-speed serial line canhave gigabits rate, but TDM transmission capacity of each high-speedserial line is limited by parallel number of high-speed driver.

[0070]FIG. 12 shows a block diagram of a center switch network board anda service board for multi-path data transmission with synchronoustransmission and store-and-forward circuit; the time sequence is shownin FIG. 14. In this diagram, suppose the TDM clock is 32 MHz, thecentral control board 10 provides the TDM frame synchronizing signal andthe TDM clock signal to every service board 11; the data is transmittedat the leading edge and sampled at the falling edge of the TDM clock.

[0071] In FIG. 12, multiple-paths TDM data are transmitted parallel tothe high-speed serial driver 15, i.e. multiple TDM data lines areconnected with the parallel data lines of the high-speed serial driver15; clock of the high-speed serial driver at transmitting end isprovided by the TDM switching circuit and the high-speed serial driverat receiving end outputs clock signal to the TDM switching circuit. TheTDM switching circuit can distribute clock signals with point-to-pointmode or bus mode.

[0072] Suppose that the high-speed serial driver has 10 parallel datalines, then its transmission capacity is 32×10=320 Mbps, i.e. it cancombine 10 data signals with 32 Mbps. Therefore, with high-speed serialline, there is enough extended redundancy for increasing service trafficat every service board.

[0073] In FIG. 14, the Fri (i=1, 2, 3 . . . ) represents frames, whichis 8 k frame and has a period of 125 μs. The data transmission procedureon the high-speed serial line of FIG. 14 is shown in the following:

[0074] 1) During first frame, i.e. FR1, the TDM switching circuit attransmitting end transmits data at the leading edge of the clock; andthe parallel data lines of the high-speed serial driver sample data atthe falling edge of the clock and sends them to the high-speed serialline. The high-speed serial line transmits 8×n bits in one clock periodand 8×n×4096 bits in a frame period.

[0075] 2) During second frame, i.e. FR2, the high-speed serial driver ofthe receiving end receives synchronously the FR1 data on the high-speedline at the falling edge of the clock and sends synchronously to thestore-and-forward circuit 17 at the receiving end at the falling edge ofthe clock.

[0076] 3) During third frame, i.e. FR3, the store-and-forward circuit 17at the receiving end sends the received FR1 data to the TDM switchingcircuit at the clock leading edge strictly according to the requirementof TDM frame time sequence, and the TDM switching circuit samples thedata at the falling edge.

[0077] The above three steps performs the FR1 TDM data transmission.Repeat this procedure to perform the FR2, FR3 . . . data transmission.

[0078]FIG. 13 shows a block diagram of a center switch network board anda service board for data transmission with synchronous transmissioncircuit and the store-and-forward circuit, adding multiple frequencyclock circuit 16. The clock of the high-speed serial driver can be ntimes of the TDM switching circuit clock, wherein n is integer greaterthan 0. The objective is to make the high-speed serial driver at thetransmitting end can sample a TDM data earlier, but this is nonsense andwill increase cost and decrease reliability.

[0079] The disadvantage of this synchronous transmission andstore-and-forward mode is that there is a two-frames fixed time delay,as shown in FIG. 14. When using the center switch network board toimplement TDM concentrated switching, first the data are sent from aservice board to the center switch network board, then forwarded to theinterface board; this will cause a four frames fixed time delay, i.e.4×T_(fr), wherein the T_(fr) represents time period of one frame. Whenusing multi-frame multiplexing, i.e. taking multi-frame as a unit forevery HW, or interleaved multiplexing, i.e. interleaving multiple HWsdata in frames accordingly; the time delay will be n times of the singleframe multiplexing. So, it is inapplicable from the technology point ofview.

[0080] In summary, the four embodiments can be compared in thefollowing:

[0081] 1) In the capacity aspect, the multi-path data transmission modestaking a frame as a unit or a time-slot as a unit can bring capacity ofthe high-speed serial driver into full play and have biggest capacity,but with higher cost; the synchronous transmission and store-and-forwardmode can bring the parallel ports capacity of the high-speed serialdriver into full play and have moderate capacity and cost; thesynchronous multiplexing/de-multiplexing mode has smaller capacity andlittle cost.

[0082] 2) In the time sequence aspect, the multi-path data transmissionmodes taking a frame as a unit or a time-slot as a unit and thesynchronous transmission and store-and-forward mode are insensitive tothe clock delay, but the synchronous multiplexing/de-multiplexing modeis more sensitive to the clock delay.

[0083] The high-speed serial line used in this invention includes notonly the transmitting and receiving lines but also the TDM framesynchronous signal lines and clock lines. Signals on the high-speedserial line are differential signals.

[0084] The invention proposes a method for data transmission with thehigh-speed serial line on the backplane; and the method greatlyincreases the transmission capacity and looses the requirement of clocksynchronization; with making use of the advantages of high-speed serialsignals, the system reliability is increased greatly. The method has thefollowing effects:

[0085] 1) It is insensitive to the clock delay; in the traditional TDMdata transmission on the backplane, the clock delay brings anunsymmetrical available transmission time and therefore brings anunreliable problem in the system. In the invention, above problems aresolved.

[0086] 2) It can provide a large capacity. High-speed serial line bringsqualitative change on TDM data transmission capacity. At present thepoint-to-point high-speed serial line can have more than one Gigabitsrate, and each high-speed line can transfer TDM data with several Mbpsbandwidth.

[0087] 3) The high-speed serial line are all differential line, so theyhave good suppression ratio for common-mode interference and better EMIcharacteristic, which can guarantee data integrity during high speedtransmission.

[0088] 4) At present, the communication system is transited from thenarrowband to wideband and the wideband system uses high-speed serialline on the backplane with great capacity for data packets transmission,so using high-speed serial line on the backplane is coincidence with thetechnical development trend.

[0089] The method for data transmission with high-speed serial linebased on backplane has been described in detail, but it is not limitedin the embodiments mentioned above. Any revision or equivalentreplacement within the spirit and scope of the invention should becovered by the scope of the Claims.

1. A method for multi-path TDM data transmission based on backplane, atleast comprising: A) applying a high-speed serial line on backplane toconnect a center switch network board with each service board; B) attransmitting side, multiplexing or interleaving multi-path TDM data andthen transmitting in batch by said high-speed serial line on backplane;at receiving side, serial receiving said TDM data and thende-multiplexing or de-interleaving to TDM data of each path.
 2. Themethod according to claim 1, wherein step B) comprising: at transmittingside, multiplexing or interleaving multi-path TDM data by taking a frameas a unit, and then transmitting in batch by said high-speed serial lineon backplane; at receiving side, de-multiplexing or de-interleaving datareceived by the high-speed serial line to TDM data of each path bytaking a frame as a unit; said data serial transmitting and receivingtaking the TDM clock as sampling clock.
 3. The method according to claim1,wherein step B) comprising: at transmitting side, multiplexing orinterleaving multi-path TDM data by taking a time-slot as a unit, andthen transmitting in batch by said high-speed serial line on backplane;at receiving side, de-multiplexing or de-interleaving data received bythe high-speed serial line to TDM data of each path by taking atime-slot as a unit; said data serial transmitting and receiving takingTDM clock as sampling clock.
 4. The method according to claim 1, whereinstep B) comprising: at transmitting side, multiplexing or interleavingmulti-path TDM data by taking a bit as a unit, and then transmitting inbatch by said high-speed serial line on backplane; at receiving side,de-multiplexing or de-interleaving data received by the high-speedserial line to TDM data of each path by taking a bit as a unit; saiddata serial transmitting and receiving taking n multiple of TDM clock assampling clock, wherein n is an integer greater than zero.
 5. The methodaccording to claim 4, wherein multiplexing or interleaving of multi-pathTDM data comprising: converting multi-path TDM data from parallel toserial by a high-speed serial driver, and then sending to saidhigh-speed serial line on backplane; at receiving side, said high-speedserial driver synchronously receiving said data, makingserial-to-parallel conversion, and then sampling each path of TDM dataaccording to TDM frame synchronization signal.
 6. The method accordingto claims 2, wherein TDM frame synchronization signal and clock signalat receiving side are distributed by a point-to-point mode or a busmode.
 7. A TDM bridge connector to implement the method according toclaim 1, the bridge connector at least includes: a TDM high-speed serialtransmitting adaptive circuit, connecting with data signal of a TDMswitching circuit on its receiving end and connecting with saidhigh-speed serial line on its transmitting end, receiving multi-path TDMdata from said TDM switching circuit, and sending to said high-speedserial line after multiplexing or interleaving and adapting; a TDMhigh-speed serial receiving adaptive circuit, connecting with saidhigh-speed serial line on its receiving end and connecting with datasignals of said TDM switching circuit on its transmitting end, receivingserial data sent from the high-speed serial line, and sending to saidTDM switching circuit after adapting and de-multiplexing orde-interleaving; and a clock control circuit, connecting with the clockand sync signal of said TDM switching circuit, providing clock and syncsignal.
 8. The TDM bridge connector according to claim 7, whereinhigh-speed serial transmitting adaptive circuit further includes: a TDMreceiving interface, connecting with data signal of said TDM switchingcircuit, and receiving multi-path TDM data transmitted by the TDMswitching circuit; a store-and-forward circuit, converting said receivedmulti-path TDM data to one path serial data; a high-speed serialtransmitting interface, connecting with said high-speed serial line onbackplane, sending serial data to said high-speed serial line afteradapting; wherein high-speed serial receiving adaptive circuit furtherincludes: a high-speed serial receiving interface, connecting with saidhigh-speed serial line on backplane, receiving serial data transmittedby the high-speed serial line; a store-and-forward circuit, convertingreceived serial data to multi-path TDM data; and a TDM transmittinginterface, connecting with said TDM switching circuit, sendingmulti-path TDM data to said TDM switching circuit.
 9. The TDM bridgeconnector according to claim 7, wherein high-speed serial transmittingadaptive circuit further includes: a TDM receiving interface, connectingwith data signal of said TDM switching circuit, receiving multi-path TDMdata transmitted by the TDM switching circuit; a parallel-to-serialcircuit, converting said received multi-path TDM data to one path serialdata; a high-speed serial transmitting interface, connecting with saidhigh-speed serial line on backplane, sending serial data to saidhigh-speed serial line after adapting; wherein high-speed serialreceiving adaptive circuit further includes: a high-speed serialreceiving interface, connecting with said high-speed serial line onbackplane, receiving serial data transmitted by the high-speed serialline; a serial-to-parallel circuit, converting received serial data tomulti-path TDM data; and a TDM transmitting interface, connecting withsaid TDM switching circuit, sending TDM data to said TDM switchingcircuit.
 10. The TDM bridge connector according to claim 9, whereinhigh-speed serial transmitting adaptive circuit is a high-speed serialdriver; wherein high-speed serial receiving adaptive circuit is ahigh-speed serial driver.
 11. The TDM bridge connector according toclaims 9, wherein high-speed serial transmitting adaptive circuitfurther includes a clock multiple frequency circuit, multiplying saidTDM switching circuit clock signal and providing a multiple frequency asa high-speed serial transmission clock signal; wherein high-speed serialreceiving adaptive circuit further includes a clock multiple frequencycircuit, multiplying said TDM switching circuit clock signal andproviding a multiple frequency as a high-speed serial receiving clocksignal.
 12. The TDM bridge connector according to claim 10, saidhigh-speed serial receiving adaptive circuit further includes astore-and-forward circuit connecting with said high-speed serial driver.13. The TDM bridge connector according to claim 12, said high-speedserial transmitting adaptive circuit further includes a clock multiplefrequency circuit, multiplying said TDM switching circuit clock signaland providing a multiple frequency as a high-speed serial transmittingclock signal.
 14. The TDM bridge connector according to claim 7, saidhigh-speed serial line includes a downward transmission line from saidcenter switch network board to service boards and an upward transmissionline from service boards to said center switch network board.
 15. TheTDM bridge connector according to claims 7, said high-speed serial lineincludes a TDM data transmission line, a TDM data receiving line, a TDMframe sync line and a clock line.